| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay circuit in which a delay signal having a long delay time can be highly accurately generated without increasing an arrangement area. <P>SOLUTION: A delay circuit of the present invention comprises circuits of a four-stage configuration cascaded to sequentially transmit an input signal Sin having an edge, and a common delay circuit 3 for delaying transmission signals of the respective stages, wherein the input signal Sin is input to a first-stage input side circuit 11, and transmission signals T1-T3 delayed by the pre-stage circuit are input to second-fourth stage input circuits 12-14. In the circuit of each stage, routing control is performed so that the common delay circuit 3 is connected into a signal route during a predetermined period of time from a timing of the edge of the input signal to a timing of the edge of the transmission signal delayed by the common delay circuit 3 in the relevant circuit and the common delay circuit 3 is disconnected out of the signal route during the other period of time, and delay signals D1-D4 resulting from delaying the input signal Sin just for 1-4 multiples of a unit delay time Δt in each stage can be extracted from the 1st-4th stage circuits. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
