| 摘要 |
<p>In a DDR mode, when 1 is subtracted from the initial latency (L=3), the (L-1) count signal BRDYB is reversed to a low level. Thus, the delayed signal S(N1BD)/S(N1D) having an opposite phase to the signal S(N1)/S(N1B) is outputted and the internal clock CKI becomes high level during the high level periods of them. This is executed in synchronization with the both edges of the external clock CLK and output of doubled frequency is started. The internal clock CKI is switched to the doubled frequency in the external clock cycle immediately before completion of the initial latency count during the initial latency count period. Moreover, the valid flag RDY transits to the high level in the second cycle of the doubled frequency.</p> |
