PARALLEL SIMULATION METHOD FOR RAPID VERIFYING DESIGN OF SEMICONDUCTOR,申请号KR20040117803-传众专利搜索

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发明名称	PARALLEL SIMULATION METHOD FOR RAPID VERIFYING DESIGN OF SEMICONDUCTOR
摘要
申请公布号	KR100594593(B1)	申请公布日期	2006.06.21
申请号	KR20040117803	申请日期	2004.12.31
申请人	ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE;HOSEO UNIVERSITY ACADEMIC COOPERATION FOUNDATION	发明人	LEE, YOON SIK;KIM, WOO SUNG
分类号	H01L21/00	主分类号	H01L21/00
代理机构		代理人
主权项
地址

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