发明名称 |
EEPROM device having selecting transistors and method fabricating the same |
摘要 |
An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
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申请公布号 |
US2006120194(A1) |
申请公布日期 |
2006.06.08 |
申请号 |
US20060336751 |
申请日期 |
2006.01.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SHIN KWANG-SHIK;KIM HAN-SOO;HUR SUNG-HOI |
分类号 |
G11C7/00;H01L21/8247;G11C11/34;H01L27/10;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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