| 摘要 |
On a channel region enclosed by a pair of diffusion layers 13 A, 13 B, a first insulating layer 15 , a charge accumulative layer 17 , and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19 , two control gate layers 21 A, 21 B spaced across a gap G 1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17 , the charges injected depend on the writing voltage applied in control gate layers 21 A, 21 B and can be localized beneath the control gate layers 21 A, 21 B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21 A, 21 B, so that multi-value storage in the memory cell can be realized.
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