| 摘要 |
A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.
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