Semiconductor memory cell reading circuit, has PMOS transistors connected to recopying and reference transistors, parallel to respective control transistors, and NMOS transistors connected in series to respective PMOS transistors

摘要

The circuit has intermediate PMOS transistors (P4, P5) connected to recopying and reference transistors (P2, P1) of a current mirror circuit, parallel to control transistors (N2, N1) respectively. The gates of the transistors (P4, P5) are connected to a fixed potential. Polarization NMOS transistors, whose gates are connected to a constant polarization potential, are connected in series respectively to the transistors (P4, P5). An independent claim is also included for an integrated circuit comprising a semiconductor memory cell reading circuit.