发明名称 |
Method and apparatus of fault diagnosis for integrated logic circuits |
摘要 |
In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input signal lines and the output signal lines, different symbols are injected into fanout branches of one faulty candidate of the gates.
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申请公布号 |
US2006107157(A1) |
申请公布日期 |
2006.05.18 |
申请号 |
US20050184830 |
申请日期 |
2005.07.20 |
申请人 |
KYUSHU INSTITUTE OF TECHNOLOGY |
发明人 |
WEN XIAOQUING;KAJIHARA SEIJI |
分类号 |
G01R31/28;G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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