发明名称 LOGIC VERIFICATION DEVICE FOR LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make the same verification pattern generation device available to a different verification object without change in logic verification of a logic circuit. SOLUTION: The verification pattern generation device is divided to a transfer pattern generation device performing pattern generation in a transfer unit such as write or read, and a circuit operation simulation device simulating a circuit inputting a signal to a logic circuit of a verification object. The circuit operation simulation device receives a pattern of a transfer unit from a regulated interface, and gives it to the logic circuit of verification object at a regulated signal time. When the verification pattern is given to a different logic circuit of verification object, this device can be used without change of the transfer pattern generation device only by changing the circuit operation simulation device. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006127016(A) 申请公布日期 2006.05.18
申请号 JP20040312272 申请日期 2004.10.27
申请人 CANON INC 发明人 SAKATA KAZUAKI
分类号 G06F17/50;G01R31/3183 主分类号 G06F17/50
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