| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve the planarity of an insulator film that is polished using a CMP method. <P>SOLUTION: A wiring 10 is formed on the upper layer of an interlayer insulator film 9 which covers MISFETQ1 formed on the main surface of a semiconductor substrate 1, and a dummy wiring 11 is disposed in a region where the distances between the wirings 10 are large. In addition, the dummy wiring 11 is also disposed in a scribed region. Further, the dummy wiring 11 is not disposed in the surrounding regions of bonding pads and markers. In addition, a dummy gate wiring is disposed at the gate electrode of MISFET and at the same layer. In addition, a dummy region is directed to an isolation region of shallow groove element. After these dummy members have been provided, the insulator film is planarized by using CMP method. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
