发明名称 |
Via structure for semiconductor chip |
摘要 |
A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.
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申请公布号 |
US7042094(B2) |
申请公布日期 |
2006.05.09 |
申请号 |
US20040771000 |
申请日期 |
2004.02.02 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
KOTHANDARAMAN CHANDRASEKHARAN |
分类号 |
H01L23/48;H01L23/485;H01L23/52;H01L23/522;H01L29/40 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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