Single polysilicon process for DRAM

摘要

A method of fabricating a DRAM cell, comprising the following steps. A substrate is provided. An isolation structure is formed within the substrate. The substrate is patterned to form nodes adjacent the isolation structure. Doped regions are formed with the substrate adjacent the nodes. A gate dielectric layer is formed over the patterned substrate, lining the nodes. A conductive layer is formed over the gate dielectric layer, filling the nodes. The conductive layer is patterned to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls. Source/drain regions are formed adjacent the word lines.