| 摘要 |
PROBLEM TO BE SOLVED: To provide an interface circuit which outputs a signal in synchronization with a clock signal of a reception circuit regardless of a state of the clock signal of a transmission circuit after a data output. SOLUTION: An interface circuit is provided with a FIFO memory 11 to which output data of a transmission circuit is written, an address storing circuit 12 in which the address of the output data written in the FIFO memory 11 is sequentially stored, a first storing circuit 13 receiving an address stored in the address storing circuit 12 at fixed intervals set on the basis of the bit number of a single packet of the output data, a second storing circuit 23 receiving the address stored in the first storing circuit 13 at fixed intervals, an address reading circuit 22 sequentially reading the address stored in the second storing circuit 23, and a conversion circuit 21 inputting data read from the FIFO memory 11 based on the address read by the address reading circuit 22 and outputting data serial/parallel converted to a reception circuit 3. COPYRIGHT: (C)2006,JPO&NCIPI
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