| 摘要 |
Presented is an integrated circuit configuration for triggering single power semiconductor switches, or power semiconductor switches in half-bridge configuration. The circuit configuration consists of a first integrated trigger chip having a plurality of function groups comprising at least one first level shifter for a switch at higher potential and at least one second integrated trigger chip having a plurality of function groups comprising at least one second level shifter and a driver for this switch. The at least one trigger chip is connected downstream of the first trigger chip, the ground potential of the second trigger chip is at the output potential of the level shifter of the first trigger chip, and the trigger chips are arranged in a common housing with suitable isolation of the trigger chips against each other. |
