| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a delay time of a flip-flop circuit. <P>SOLUTION: A master circuit 1 and a slave circuit 2 are a latch circuit of an identical configuration. A first upper stage differential circuit composed of Q1, Q2, R1, and R2 acquires a voltage level of output terminals 7 and 8. A second upper stage differential circuit composed of Q3, Q4, R1, and R2 holds a voltage level outputted by the first upper stage differential circuit. A lower stage differential circuit composed of Q6 and Q7 responds to a complementary clock signal impressed to input terminals 3 and 4, and operates the first and the second upper stage differential circuits. During a hold operation when Q7 become ON, Q5 shunts current flown by Q3 or Q4 to reduce a voltage drop. As the result, a delay time for transition to an acquisition operation can be reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
