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发明名称
Circuit arrangement to generate a clock signal for a sigma-delta analog-to-digital converter
摘要
申请公布号
EP1501195(B1)
申请公布日期
2006.04.19
申请号
EP20030016974
申请日期
2003.07.25
申请人
SIEMENS SCHWEIZ AG
发明人
STOLL, WALTER
分类号
G01R23/15;H03M3/02;G01R23/10;G01R31/3167;G01R35/00;G06F3/05;G06M3/02
主分类号
G01R23/15
代理机构
代理人
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