发明名称 Data processing apparatus and slave interface mechanism for controlling access to a slave logic unit by a plurality of master logic units
摘要 The present invention provides a data processing apparatus and slave interface mechanism for controlling access to a slave logic unit by a plurality of master logic units. The data processing apparatus comprises a first bus for coupling a first master logic unit with a plurality of slave logic units to enable the first master logic unit to issue a first transfer request to any of said slave logic units, and a second bus for coupling a second master logic unit with a subset of said plurality of slave logic units to enable the second master logic unit to issue a second transfer request to any of the slave logic units in the subset. A slave interface mechanism is then associated with each slave logic unit in the subset and comprises switching logic arranged to connect either the first bus or the second bus to the corresponding slave logic unit to enable either the first transfer request or the second transfer request to be routed to that slave logic unit. By this approach, unrelated transfer requests can be processed in parallel.
申请公布号 US7031337(B2) 申请公布日期 2006.04.18
申请号 US20010845329 申请日期 2001.05.01
申请人 ARM LIMITED 发明人 MARTIN SAN JUAN MARTIN
分类号 G06F13/28;H04J3/02;G06F13/00;G06F13/364;G06F13/40;G06F15/16;H04L12/40 主分类号 G06F13/28
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