发明名称 METHOD AND STRUCTURE FOR TESTING SEMICONDUCTOR WAFER PRIOR TO EXECUTION OF FLIP CHIP BUMPING PROCESS
摘要 <P>PROBLEM TO BE SOLVED: To provide a method and structure for testing a semiconductor wafer prior to the execution of flip chip bumping process. <P>SOLUTION: An interface assembly (20) for testing a semiconductor wafer prior to the execution of a flip chip bumping process and its method are provided. The interface assembly is equipped with a flip chip-bonding pad (24) having a region for the execution of a bumping process (28). A testing pad (22), which is integrated with the bonding pad, is equipped with a probe region for the execution of a wafer level testing (26) prior to the execution of the bumping process. As a result of integration of the bonding pad with the testing pad, for example, the introduction of propagation delay to passing test signals can be avoided, thereby improving the accuracy and reliability of wafer testing results. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006100828(A) 申请公布日期 2006.04.13
申请号 JP20050279267 申请日期 2005.09.27
申请人 AGERE SYSTEMS INC 发明人 BACHMAN MARK ADAM;CHESIRE DANIEL PATRICK;KOOK TAEHO;MERCHANT SAILESH M
分类号 H01L21/66;H01L21/60;H01L23/485;H01L23/58 主分类号 H01L21/66
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