发明名称 LATERAL MOS TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To reduce wiring resistance, wiring capacity, and a chip area. SOLUTION: An SOI substrate 30 is composed by forming an n<SP>-</SP>type silicon layer 33 on a silicon oxide film 32 after forming the silicon oxide film 32 on a silicon substrate 31. A drain region 35 is formed so as to reach the silicon oxide film 32 from the surface of the silicon layer 33. A drain electrode 42 is formed by being electrically in contact with the rear face of the SOI substrate 30. A conductor plug 41 is extended in the silicon substrate 31 by penetrating the drain region 35 and the silicon oxide film 32 from the surface of the drain region 35, and formed by being electrically in contact with the drain region 35 and the silicon substrate 31. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006100621(A) 申请公布日期 2006.04.13
申请号 JP20040285686 申请日期 2004.09.30
申请人 NEC COMPOUND SEMICONDUCTOR DEVICES LTD 发明人 YAMAGISHI KAZUO
分类号 H01L29/786;H01L21/336;H01L29/41 主分类号 H01L29/786
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