| 摘要 |
This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular memory block after a failure is detected in the block. The test system which tests writing and erasing as a unit of block in the memory under test. The test system includes a register provided for each memory under test for holding a first failure generated in a particular block at a first control signal from a pattern generator, establishes a pass result for the particular block for test cycles after the first failure, thereby treating any failure result for the particular block as the pass result thereafter; and resets the register at a cycle specified by a second control signal from the pattern generator to release the pass result.
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