发明名称 |
Masking arrangement and method for producing integrated circuit arrangements |
摘要 |
A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.
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申请公布号 |
US2006073397(A1) |
申请公布日期 |
2006.04.06 |
申请号 |
US20050244857 |
申请日期 |
2005.10.06 |
申请人 |
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发明人 |
FREUND JOHANNES;STETTER MICHAEL |
分类号 |
G03C5/00;G03F;G03F1/00;G03F1/14;G03F7/20;G03F9/00;H01L23/544 |
主分类号 |
G03C5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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