发明名称 ON-CHIP LOGIC ANALYZER
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem wherein the use of an externally connected logic analyzer has been a factor causing a memory capacity shortage when status values in an LSI are recorded and making debugging work inefficient. <P>SOLUTION: In the case where waveform data of monitor signals outputs different status values, memory addresses are counted up, and its status values is written in a memory 5. In the case of outputting continuous and identical status values, the status values are compressed and processed and a count value of the number of repetitions of the identical data is superposed on a count value of the number of items of data having different values and recorded. While a trigger is not generated in waveform data, memory addresses and memory data are repeatedly overwritten in memory effective addresses. When a trigger is generated, a counter of a count signal generating circuit 13 is decremented. When the counter is zeroized, a memory writing operation is halted to report a notice of a status of a signal of completion. A shift is made to memory read of data stored in the memory on the basis of information on the status. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006090727(A) 申请公布日期 2006.04.06
申请号 JP20040273294 申请日期 2004.09.21
申请人 NEC ENGINEERING LTD 发明人 TSUCHIDA YASUSHI
分类号 G01R31/28;G06F11/22;H01L21/822;H01L27/04 主分类号 G01R31/28
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