REDUCTION OF SHEET RESISTANCE OF PHOSPHORUS IMPLANTED POLY-SILICON

摘要

There is a process for reducing the sheet resistance of phosphorus-implanted poly­silicon. In an example embodiment, there is an MOS transistor structure (300). The structure has a gate region, drain region and a source region. A method (220) for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon (221) at a predetermined temperature onto the gate region. An amorphizing species is implanted (222) into the intrinsic amorphous silicon. Phosphorus species are then implanted (223) into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.