| 摘要 |
PROBLEM TO BE SOLVED: To suppress an excessive rise in a DC output voltage generated by a power factor improving circuit. SOLUTION: An integrated circuit section 41 of the power factor improving circuit has an error amplifier 41a which outputs a differential voltage between the charging voltage of a capacitor 35 and a predetermined voltage, a timing setter 40B which sets the on/off-timing of a switching element 36, a comparator 41e, and a switch 41f. When an instantaneous power interruption is generated and the charging voltage of the capacitor 35 is decreased, the comparator 41e detects it and turns on the switch 41f. Therefore, the capacitor 42 is discharged, and a differential voltage inputted in the timing setter 40B is reset to 0. At the electrical reset, a period when the switching element 36 is turned on is shortened, thus suppressing the charging voltage of the capacitor 35 from excessively rising. COPYRIGHT: (C)2006,JPO&NCIPI
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