发明名称 Methods for memory assignment schemes and architecture for shareable parallel memory module based internet switches
摘要 Systems and methods are described for high-speed memory assignment schemes for routing packets in a sharable parallel memory module based switch system. A method includes receiving a parameter, determining availability of memory location, determining if an available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available. Systems of the present invention provides hardware and/or software based components for implementing the steps of receiving a parameter, determining available memory location, determining if available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available.
申请公布号 US2006062232(A1) 申请公布日期 2006.03.23
申请号 US20050213626 申请日期 2005.08.26
申请人 BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM 发明人 KUMAR SANJEEV
分类号 H04L12/56 主分类号 H04L12/56
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