发明名称 |
Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length |
摘要 |
The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.
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申请公布号 |
US7017010(B2) |
申请公布日期 |
2006.03.21 |
申请号 |
US20030338398 |
申请日期 |
2003.01.08 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LA ONE-GYUN |
分类号 |
G06F12/00;G11C11/401;G11C7/10;G11C8/04;G11C8/12;G11C11/4063;G11C11/408;G11C11/409;G11C11/4096 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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