| 摘要 |
In accordance with the present invention, an integrated circuit system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably connected to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In one embodiment of the invention the first level of coherency is implemented using a "snoopy" protocol and the second level of coherency is a directory-based coherency scheme. In some embodiments of the invention, the directory-based coherency scheme is implemented using a centralized memory and directory architecture. In other embodiments of the invention, the second level of coherency is implemented using distributed memory and a distributed directory. In another alternate embodiment of the invention, a third level of coherency is implemented for transfer of data externally from the integrated circuit.
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