发明名称 Synthesizing a pixel clock with extremely close channel spacing
摘要 A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M 1 *M 2 )/(N 1 *N 2 ). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.
申请公布号 US7013403(B2) 申请公布日期 2006.03.14
申请号 US20020199473 申请日期 2002.07.19
申请人 SUN MICROSYSTEMS, INC. 发明人 NAEGLE NATHANIEL DAVID
分类号 G06F1/04;G09G5/00;G09G5/18;H03L7/23;H04N5/12 主分类号 G06F1/04
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