发明名称 Methods of manufacture of a via structure comprising a plurality of conductive elements, semiconductor die, multichip module, and system including same
摘要 Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed therethrough. At least one seed layer may be formed, patterned, and a metal may be deposited thereon to form a plurality of conductive elements. Alternatively, the at least one through-hole may be substantially filled with a dielectric material and a plurality of smaller through-holes may be formed therein and then filled with conductive material to form a plurality of conductive elements. Alternatively, at least one cavity may be formed into a substrate and a plurality of conductive nanotubes or other protruding structures may be formed therein. The substrate may be thinned to form at least one through-hole and a plurality of laterally separated conductive elements extending therethrough. Semiconductor dice, substrates, as well as multichip modules having dice including multiconductor vias, systems including same, and methods of manufacture are also disclosed.
申请公布号 US2006043598(A1) 申请公布日期 2006.03.02
申请号 US20040931959 申请日期 2004.08.31
申请人 发明人 KIRBY KYLE K.;FARNWORTH WARREN M.
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
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