发明名称 |
DIGITAL PHASE AQUISITION WITH DELAY-LOCKED LOOP |
摘要 |
A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and sychronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition. The data sample phase associated with the highest relative quality value integrated over time is then used to recover the incoming (i.e., optimally phased) data signal.
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申请公布号 |
WO9833292(A1) |
申请公布日期 |
1998.07.30 |
申请号 |
WO1998US00849 |
申请日期 |
1998.01.15 |
申请人 |
ERICSSON INC. |
发明人 |
ELLERSICK, WILLIAM, F.;GELLER, WILLIAM, L.;SODERBERG, PAULMER, M. |
分类号 |
H04L7/033;H04L7/04;(IPC1-7):H04L7/033 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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