发明名称 PIPELINED ANALOG/DIGITAL CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide a pipelined analog/digital converter having the high degree of freedom in design and reduced circuit scale/power consumption. SOLUTION: Bit blocks 10-13 each having A/D a converter (AD1-AD3) for converting an analog signal into a digital code of a distributed predetermined bit, a D/A converter (DA1-DA3) for converting the digital code into an analog signal and an amplifier (AMP0-AMP3) are connected in cascade. The amplification unit of each of the bit blocks amplifies the difference between an analog signal from the prestage and an analog signal from each of the D/A converters to sequentially supply to the next stage bit block. In that case, amplification units of the adjacent bit blocks share an amplifier (amplifier share) to ensure a high DC gain. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006054608(A) 申请公布日期 2006.02.23
申请号 JP20040233757 申请日期 2004.08.10
申请人 SONY CORP 发明人 ONO KOICHI
分类号 H03M1/44 主分类号 H03M1/44
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