发明名称 |
Low latency switch architecture for high-performance packet-switched networks |
摘要 |
A low latency switch architecture for high performance packet-switched networks which is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output simultaneously.
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申请公布号 |
US2006039370(A1) |
申请公布日期 |
2006.02.23 |
申请号 |
US20050040298 |
申请日期 |
2005.01.12 |
申请人 |
ROSEN WARREN;SUKHTANKAR SATYEN;LACHENMAIER RALPH N |
发明人 |
ROSEN WARREN;SUKHTANKAR SATYEN;LACHENMAIER RALPH N. |
分类号 |
H04L12/56 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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