发明名称 |
Memory array with staged output |
摘要 |
Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.
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申请公布号 |
US7002873(B2) |
申请公布日期 |
2006.02.21 |
申请号 |
US20030739268 |
申请日期 |
2003.12.19 |
申请人 |
INTEL CORPORATION |
发明人 |
JOURDAN STEPHAN J.;PHELPS BOYD S.;YUKER CHRIS E. |
分类号 |
G11C8/00;G11C7/10;G11C11/413 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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