| 摘要 |
An analog delay locked loop, an operating method thereof, a circuit and a method for recovering clock data, a phase locked loop, and an operating method thereof are provided to reduce a locked time by controlling resolution according to the remaining time up to the locking. An analog delay locked loop includes a flag signal generator(510) and a clock alignment unit(520). The flag signal generator generates a flag signal enabled according to the remaining time before the locking of the delay locked loop. The clock alignment unit includes a delay model unit, a phase comparator, a charge pump unit, a loop filter unit and a voltage control delay line unit. The delay model unit models the delay time between the external clock and the internal clock. The phase comparator compares the output of the delay model unit with the phase of the internal clock. The charge pump unit outputs the charging current or the discharge current in response to the output of the phase comparator. The loop filter unit outputs the control voltage in response to the charging current and the discharge current. The voltage control delay line unit outputs the delay value of the internal clock in response to the control voltage. |
