| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance the debug efficiency of a processor. <P>SOLUTION: A debug mechanism 133 stores OPCODEs for 6 cycles in the past in a shift register 134 and a scan part 135 scans and reads the OPCODEs stored in the shift register 134. In addition, the debug mechanism may also be constituted so as to input a REQUEST_VALID signal and to store the OPCODEs in the shift register only when a value of the REQUEST_VALID signal is "1". Moreover, in the case of a processor having a plurality of arithmetic units, the debug mechanism may also be constituted so as to store OPCODEs of the plurality of arithmetic units. Moreover, the debug mechanism may also be constituted so as to select and store the OPCODEs or RUPT_CODEs. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
