| 摘要 |
PROBLEM TO BE SOLVED: To optimize rule distribution and to reduce man-hour required for performing design verification when performing design rule check by parallel processing. SOLUTION: A design rule check execution device 100 executes design rule check by applying a plurality of design rules for verification in relation to a layout pattern specifying structure of a semiconductor integrated circuit. The device comprises a verification time database 1 for holding a standard verification time of each design rule among a plurality of design rules, a verification time estimation unit 4 for estimating the verification time of each design rule among the plurality of the design rules to be applied to the semiconductor integrated circuit based on the standard verification time, a rule distribution unit 5 for distributing the verification of the plurality of the design rules to a plurality of verification execution units based on the verification time of each design rule estimated by the verification time estimation unit, and a plurality of verification execution units 7 for each executing the verification of the design rules distributed by the rule distribution unit. COPYRIGHT: (C)2006,JPO&NCIPI
|
