发明名称 CHARGE TRAPPING NON-VOLATILE MEMORY WITH TWO TRAPPING LOCATIONS PER GATE, AND METHOD FOR OPERATING SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To provide memory technology for a non-volatile memory which is manufactured easily, and corresponds to the application of high density. <P>SOLUTION: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates 50, 51 arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations, beneath each of all or some of the gates in the plurality of gates 50, 51. Circuitry for conducting source 55 and drain 56 bias voltages to the semiconductor body near a first gate 50 and a last gate 51 in the series, and circuitry to conduct gate bias voltages to the plurality of gates are provided. The multiple-gate memory cell includes a continuous, multiple-gate channel region 58 beneath the plurality of gates 50, 51 in the series, with charge storage locations between some or all of the gates. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006024930(A) 申请公布日期 2006.01.26
申请号 JP20050194520 申请日期 2005.07.04
申请人 MACRONIX INTERNATL CO LTD 发明人 YEH CHIH CHIEH
分类号 H01L21/8247;G11C16/04;G11C16/06;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
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