| 摘要 |
The invention relates to a method for the distributed fault-tolerant clock pulse generation in hardware systems, especially in VLSI chips, systems-on-a-chip, IP-cores and PCBs, said method being characterised in that a) the system clock pulse is formed in a distributed manner by means of a plurality of intercommunicating, fault-tolerant clock pulse synchronisation algorithms (TS-Algs), without using external or internal clock pulse oscillators, by i) any number of such TS-Algs exchanging information between each other by means of a network (TS-Net) subjected to any permanent and transient errors, ii) each TS-Alg is associated with at least one functional unit (Fu1, Fu2, ...), generating the local clock pulse thereof; b) all local clock pulses are maintained with a guaranteed frequency synchronisation, in such a way that any two local clock pulse signals differ in any time interval at the most by a given constant number of clock pulse periods, such that a global system clock pulse can be derived from each local clock pulse by the downstream connection of suitable clock pulse conversion circuits (dividers etc.), said system clock pulse enabling the global synchronous communication of any functional units on the chips; c) a specified number of transient and/or permanent errors can occur in the TS-Algs or in the TS-Net without affecting the clock pulse generation and/or the synchronisation accuracy; and d) the system clock pulse automatically reaches the maximum possible frequency determined by the used production technology, the Placement & Routing of the TS-Algs and the TS-Nets, and the current operating conditions (temperature, supply voltage etc.). |
