发明名称
摘要 In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.
申请公布号 JP2006501661(A) 申请公布日期 2006.01.12
申请号 JP20040540920 申请日期 2003.09.15
申请人 发明人
分类号 H01L21/60;H01L23/13;H01L23/50;H05K1/02;H05K3/34 主分类号 H01L21/60
代理机构 代理人
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