DATA PROCESSING UNIT AND COMPATIBLE PROCESSOR

摘要

A processor maintaining backward compatibility with a previous generation processor is provided. When an operation is performed in a current generation processor 100 for writing a value to an address, which is the same address as assigned to a zeroth area access cycle number register of a previous generation processor 500, the same value is written to a zeroth area random access cycle number register 170, and a zeroth area page size register 190 is set to "0" (page size = 0 byte) such that the page mode is disabled. On the other hand, when an operation is executed by the current generation processor 100 for writing a value to an address, which is the same address as assigned to a first and a second area access cycle number register of the previous generation processor 500, the same value is written to both a first area random access cycle number register 171 and a second area random access cycle number register 172, and a first area page size register 191 and a second area page size register 192 are set to "0" such that the page mode is disabled.