High performance user configurable coprocessor

摘要

A simple data processing unit is described comprising a register file, a register scoreboard, memories, a plurality of executions units. This data processing unit has an interface to a plurality of coprocessors together with the data and control signals to enable said coprocessors to operate concurrently with one another and with the main execution unit relying on the register scoreboard to maintain the correct pipeline synchronization. The number and function of the coprocessors can be configured very easily by someone who is not familiar with the processor architecture or the implementation (for example a client of the processor IP).