发明名称 |
Practical method for hierarchical-preserving layout optimization of integrated circuit layout |
摘要 |
The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
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申请公布号 |
US6986109(B2) |
申请公布日期 |
2006.01.10 |
申请号 |
US20030438625 |
申请日期 |
2003.05.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALLEN ROBERT J.;HENG FOOK-LUEN;LVOV ALEXEY Y.;MCCULLEN KEVIN W.;PERI SRIRAM;TELLEZ GUSTAVO E. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
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