| 摘要 |
PROBLEM TO BE SOLVED: To shorten the manufacturing period of an LSI chip and reduce the manufacturing cost of the LSI chip by simply and efficiently designing the layout of the LSI chip. SOLUTION: Residual global wiring data 701 and 702 formed to third wiring-layer data 303, and fixed-signal conductor section data 402 formed to fifth wiring-layer data 305 are connected. A connection 207 concretely generates connecting-signal conductor data 901 and 902 using the difference of the height information of the fifth wiring-layer data 305 and the third wiring-layer data 303 as a length. The connecting-signal conductor data 901 and 902 are wired at points of ends of the residual global wiring data 701 and 702 generated by erasing processing by an eraser 206 and the end of the fixed-signal conductor data 402. COPYRIGHT: (C)2006,JPO&NCIPI
|
