| 摘要 |
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The floating gate transistor can be programmed by trapping charge on the floating gate.
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