发明名称 Dual damascene trench formation to avoid low-K dielectric damage
摘要 A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
申请公布号 US2006003576(A1) 申请公布日期 2006.01.05
申请号 US20040882058 申请日期 2004.06.30
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 YEH CHEN-NAN;WU TSIAO-CHEN;CHEN CHAO-CHENG
分类号 H01L21/4763 主分类号 H01L21/4763
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