发明名称 |
Latch-up prevention for memory cells |
摘要 |
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V<SUB>CC </SUB>through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
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申请公布号 |
US2005286288(A1) |
申请公布日期 |
2005.12.29 |
申请号 |
US20050216665 |
申请日期 |
2005.08.31 |
申请人 |
PORTER JOHN D;THOMPSON WILLIAM N |
发明人 |
PORTER JOHN D.;THOMPSON WILLIAM N. |
分类号 |
G11C5/06;G11C11/412;H01L21/8234;H01L21/8238;H01L21/8244;H01L27/11;(IPC1-7):G11C5/06 |
主分类号 |
G11C5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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