发明名称 |
Memory and method for employing a checksum for addresses of replaced storage elements |
摘要 |
A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2<SUP>m </SUP>bit row or 2<SUP>n </SUP>bit column of a fuse array; a vector generator operable to produce a 2<SUP>n </SUP>bit row vector based on the rows of the fuse array and to produce a 2<SUP>m </SUP>bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.
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申请公布号 |
US6981175(B2) |
申请公布日期 |
2005.12.27 |
申请号 |
US20010967008 |
申请日期 |
2001.09.28 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
VOLLRATH JOERG;MOORE PHILIP |
分类号 |
G06F11/00;G06F11/10;G06F11/16;G06F12/02;G11C29/00;G11C29/02;G11C29/42;H04L1/22;(IPC1-7):G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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