| 摘要 |
<p>A clock adjusting circuit is disclosed which is able to adjust automatically both the phase and pulse width of a balanced transmission clock, to be coincident with the reference clock. Phase comparison circuits (13, 14) detect the difference between the phase of a reference clock (REF) and feedback signal of clock output. Counters (15, 16) count based on the difference detected by the phase comparison circuits (13, 14), respectively. Delay circuits (11, 12) delay the clock input signals based on the counted value by the counters (15, 16). Clock output signal is obtained after selecting, by the selector (23), the result of OR or AND of the outputs of the delay circuit (11, 12).</p> |
