| 摘要 |
A synchronous semiconductor memory operating in synchronization with an external clock signal has (a) a mode selector to select one of a normal mode and a test mode, (b) a clock generator to generate, in the test mode, an internal clock signal whose frequency is higher than the frequency of the external clock signal, (c) an address generator to generate, in the test mode, internal addresses in synchronization with the internal clock signal, the internal clock signal and internal addresses being used in the test mode to carry out a test and provide test result data, and (d) an output data controller to select, in the test mode, part of the test result data and provide the selected part as output data in synchronization with the external clock signal.
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