| 摘要 |
<p>A system clock generator circuit for use in a D/A converter that allows the clock of any frequency to be inputted and also allows usage limiting-conditions to be simplified. A system clock generator circuit for use in a D/A converter for demodulating one-bit digital input data, which has been obtained by DeltaSigma modulation scheme, into analog output data in synchronism with an internal system clock and for outputting the analog output data, comprises a counter circuit for receiving external system clocks and LR clocks (LRCLK) having predetermined repetitive frequencies to count the number of the external system clocks included in one period of the LR clocks; a timing generator circuit for generating mask signals for thinning, in accordance with the count value as counted by the counter circuit, the external system clocks at predetermined thinning timings; and a mask circuit for masking the external system clocks by use of the mask signals and thinning the clocks in the masked portions to generate internal system clocks.</p> |
